Apple M4: TSMC's FinFlex helps the performance cores

For the first time, Apple is using high-performance blocks in a processor, with which the CPU cores can achieve clock frequencies of up to 4.4 GHz.

(Image: Apple)

Jun 17, 2024 at 10:00 pm CEST

3 min. read

Mac & i

By

Mark Mantel

This article was originally published in German and has been automatically translated.

For its M4 processor, Apple uses the so-called FinFlex construction kit from chip contract manufacturer TSMC to optimize different chip areas for efficiency or performance. For the first time, high-performance blocks are used for – particularly high clock frequencies of almost 4.4 GHz by Apple standards –.

Until the 3-nanometer generation (N3), TSMC only allowed the use of a single FinFET transistor layout across the entire chip. The chip developers use cell blocks for CMOS transistor pairs, i.e. interconnected PMOS and NMOS FinFETs with opposite current flow directions. In the 5 nm process N5 and its improved version N4, these were cell blocks of about 2 cells with two gate "fins" per current flow direction.

Current flows through each fin from the source to the drain side of the field-effect transistor (FET) – which is why they are called FinFETs in these manufacturing processes. The surrounding gate electrode controls the current flow within the fins.

Until now, chip designers had to decide which logic blocks they wanted to optimize their semiconductors for. With a focus on CPU cores and high clock frequencies, other parts such as the graphics unit could not be packed as compactly as would have been possible with a different orientation. Conversely, a focus on efficiency and packing density would not allow such high clock frequencies for the CPU.

Die-shot of Apple's M4 processor. — Techinsights has ground down Apple's M4 processor from an iPad Pro and created die shots of the chip structures. The performance cores with the high-performance cell blocks are outlined in yellow.

(Image: Techinsights)

Mixed-mesh transistors

However, asymmetrical designs are possible with N3 and the second 3 nm generation N3E. The analysis company Techinsights has analyzed Apple's M4 and confirms a mixture of 3-2 and 2-1 blocks.

Apple uses the 3-2 variant for the four performance CPU cores (P-cores). The cell rows consist of alternating blocks with three and two fins per current flow direction, i.e. 3-3 plus 2-2. More current flows through the pairs of 3 so that the transistors can switch faster – this effectively increases the clock frequency. The 2-pairs in between keep the leakage currents within limits.

Illustration of TSMC's FinFlex kit: The first cell block has three fins in one current flow direction, the next two. The semi-transparent blocks around it are the gate electrodes that regulate the current flow.

(Image: TSMC)

Together with design optimizations on the CPU, the performance cores achieve clock frequencies of up to 4.38 GHz. That is 8 percent more than the M3 (4.056 GHz) without the required voltage exploding.

Compact and efficient

All other components of the system-on-chip (SoC), such as the efficiency cores, GPU and AI unit, use the 2-1 blocks, which work more efficiently at lower clock frequencies and save space. This hybrid approach means that Apple can continue to operate the M4 in the current iPad Pro without a fan.

According to Techinsights, Apple first experimented with TSMC's N3(B) technology in the iPhone processor A17 Pro with the FinFlex kit. It features 2-2 and 2-1 cell blocks – the former representing a middle ground between 3-2 and 2-1 to balance clock speeds and efficiency. With the M4, the company goes one step further.

Empfohlener redaktioneller Inhalt

Mit Ihrer Zustimmmung wird hier ein externer Preisvergleich (heise Preisvergleich) geladen.

Preisvergleiche immer laden

Ich bin damit einverstanden, dass mir externe Inhalte angezeigt werden. Damit können personenbezogene Daten an Drittplattformen (heise Preisvergleich) übermittelt werden. Mehr dazu in unserer Datenschutzerklärung.