BIOS updates for Ryzen 9000 reduce latencies
With AMD's Ryzen 9 9000, the latency between two chiplets used to be unusually high. The new AGESA version 1.2.0.2 reduces it.
The increased latency only occurred with the Ryzen 9 9000 between the compute dies.
(Image: c't / chh)
Asus is the first motherboard manufacturer to distribute BIOS updates with the AMD Generic Encapsulated Software Architecture (AGESA) 1.2.0.2 for AM5 boards. The AGESA contains new microcode for Ryzen 9000 processors, which reduces the latency between the compute dies (CCDs) for the 16 and 12 cores. Other motherboard manufacturers are expected to follow soon.
With the Ryzen 9 9950X and Ryzen 9 9900X, the response times between the chiplets without a BIOS update have a latency of around 180 nanoseconds (ns) – more than twice as much as with the predecessors from the 7000 series. This can particularly reduce performance if threads frequently jump between the two compute dies, i.e. with poorly optimized software or if the operating system scheduler messes up.
The BIOS updates now reduce the latency to around 75 ns and thus to the level of the Ryzen 7000, as proven by numerous test results with the CapFrameX tool. In many benchmarks, however, the performance should only increase slightly – in the range of one to two percent and thus not noticeably.
Deliberate, but not communicated decision
Alexander Yee suggests in a comment on the Overclock.net forum that the high latency was not an oversight, but a deliberate design decision by AMD engineers. Yee is developing y-Cruncher, a (benchmark) tool for calculating countless pi decimal places and other constants.
"That was faster than I thought. I guess I can say this now that it has happened. One of the lead architects told me that the latency regression was because they changed a bunch of tuning parameters for Zen5. It helped whatever workloads they were testing against, which is why they did it. But now that the reviews are out, they realized that the change looked really bad for synthetics. So they were going to roll it back. But they said "it would take a while" due to validation."
AMD did not communicate any changes to the communication behavior between the compute dies, which is why the high latencies came as a surprise.
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