QEMU 9.1.0: Updated support for modern Intel Xeon CPUs
QEMU 9.1.0 brings further support for modern Xeon and Epyc processors. But there are also new features for ARM, RISC-V, LoongArch and even SPARC.
(Image: QEMU)
- Michael Plura
QEMU 9.1.0 is here: Compared to version 9.0.0, the free virtualization software has even received slightly more commits (2800 instead of 2700) from almost 20 percent more developers (263 instead of 220). As support for the x86 architecture is quite complete, there are only a few improvements here, especially for modern CPU functions. Instead, the innovations for the comparatively young ARM and RISC-V architectures predominate.
The Nios II platform, a 32-bit embedded architecture for Altera FPGAs, has been dropped. There is no longer a SCSI property for virtio-based block devices; virtio-scsi should be used.
New for Intel Xeon and AMD Epyc
Support for modern Intel Xeon CPUs has been expanded: In addition to Sapphire Rapids (2023) and Sierra Forrest (2024), this also includes the Icelake-v7 architecture. The update from Icelake-v3 to v7 was necessary because there was a discrepancy with the TSX feature in combination with taa-no. If the host is not susceptible to the TAA exploit (TSX Async Abort), activating TSX should improve performance. The combination of the Intel Query Processing Library (QPL) with the In-Memory Analytics Accelerator (IAA) should accelerate the migration of VMs in QEMU 9.1.0 via Compression Offload.
QEMU 9.1.0 supports AMD's Secure Encrypted Virtualization (SEV) for handling guests via the command line option -object sev-snp-guest. This requires a current Linux kernel and AMD's Epyc processors.
ARM and RISC-V with significant progress
QEMU 9.1.0 offers ARM guests additional features for FEAT_NMI, FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC, FEAT_WFxT and FEAT_Debugv8p8. The emulated SMMUv3 now supports nested page tables (two-level). The "max" CPU (ARMv8-A) and all new CPU types use a generic timer frequency of 1 GHz as standard instead of the old 62.5 MHz. Architecturally, this is mandatory from ARMv8.6 onwards. Some board models such as xilinx_zynq have received improvements.
Many additional extensions are available to RISC-V guests, and the 1.13 specification is also supported for RISC-V. 64-bit addresses can now be used in the initrd. ACPI tests are also possible. QEMU 9.1.0 now also supports debugging/GDB on RISC-V via KVM Guest Debug.
LoongArch boots EIF kernel
The Chinese LoongArch architecture, a further development based on MIPS64r6 and RISC-V, can now boot EIF kernels directly. This enclave image format is used in AWS Nitro Enclaves. Also new for LoongArch are support for KVM Guest Debug and TPMs. Even the SPARC emulation has been extended by some features (FMAF, IMA, VIS3, VIS4), which are not activated via new CPU types, but manually via -cpu <type>,+<feature>.
All changes and possible problems of QEMU 9.1.0 are documented in the changelog. The online documentation and the current source code are freely available from the developers on the QEMU project page.
(olb)