Chip production: TSMC's plans until 2027
TSMC plans to launch two new production generations in the next three years. Together with A16, particularly huge chip designs are possible.
(Image: Taiwan Semiconductor Manufacturing Co., Ltd.)
The world's leading chip contract manufacturer TSMC from Taiwan has revised its roadmap for the coming years. The next production generation N2 should still be ready for series production in 2025, but no longer with so-called backside power delivery.
TSMC now calls this technology Super Power Rail and will only introduce it with the next but one production generation A16. The chip manufacturer is following Intel's Ångström naming convention. These names still have nothing to do with the actual smallest physical structure widths on the chips, nor do the usual fantasy nanometer numbers.
Both manufacturers are implementing an important change in future chip designs: The transistors will be supplied with power from the underside of the chip to significantly increase efficiency.
Until now, power has been supplied via metal layers on the top of the chips. However, this is also where the metal layers that connect the signals of the transistors are located. Signal and current paths increasingly come into conflict as the number of transistors increases and their dimensions shrink. The rear power supply therefore creates more space for interconnection.
TSMC wants to take a different approach to Intel: instead of etching tiny holes in the silicon for the power lines (power vias), TSMC exposes the transistors on the underside. TSMC describes this design as industry-leading.
(Image: Taiwan Semiconductor Manufacturing Co., Ltd.)
N2(P) makes its nanosheet debut
Series production with A16 technology is set to begin in the second half of 2026. One year earlier, N2 and N2P will be ready, with which TSMC will introduce transistors in the Gate All Around (GAA) design, known as nanosheets in marketing speak. GAA technology replaces the long-established fin-shaped field-effect transistors (FinFETs), which TSMC introduced in 2014 with its 16 nm process (and Intel in 2012 as a tri-gate transistor in the 22 nanometer P1270 process).
TSMC is focusing on N2P – N2, like N3, is likely to be primarily intended for early adopter customers, i.e. primarily Apple.
N2P designs are said to switch 15 to 20 percent faster than N3E chips – TSMC's current 3 nm generation with the same electrical power consumption. With the same performance, electrical power consumption is predicted to drop by 30 to 40 percent. The packing density of a typical processor is expected to increase by a factor of at least 1.15.
(Image: Taiwan Semiconductor Manufacturing Co., Ltd.)
TSMC is already reporting a pleasingly high N2P chip yield of over 80 percent for test chips.
Customers do not have to choose strictly between performance and efficiency for a chip. Nanoflex, which was introduced with N3E, is also part of N2P: the nanosheet transistors can have different widths and heights in the same chip in order to trim them for either short switching times or high efficiency. For example, high-performance cores with high cells can clock particularly quickly and efficiency cores can run at a low voltage thanks to flatter cells.
A16 with a focus on power supply
The A16 process is intended to increase performance by a further 8 to 10 percent with the same electrical power consumption compared to N2P. Alternatively, the electrical power consumption is reduced by 15 to 20 percent with the same performance. The packing density should increase moderately by 7 to 10 percent.
(Image: Taiwan Semiconductor Manufacturing Co., Ltd.)
According to TSMC, the improvements in A16 are largely due to the Super Power Rail – the company appears to have made few changes to the transistor structure itself. Instead, TSMC has brought forward the introduction of A16 to 2026.
