Intel Xeon 6700E: Initially with 64 to 144 E-cores, later up to 288

The Xeon 6700E are said to be suitable for highly compacted data centers that serve web and microservices, run databases and analytics or simply connect mass storage. They also compete with ARM processors, the AMD Epyc 9004 Bergamo with up to 128 cores, and are also likely to have to contend with AMD's freshly announced Zen 5 Epycs in their lifetime, which even crank up to 192 physical cores and 384 threads.

The Epyc 6700E will be available for servers with one or two sockets, while the Xeon 6700P, which will be released later, will also serve four and eight sockets. There is currently no talk of variants with integrated HBM memory à la Xeon CPU Max. These were left out of the Emeralds Rapids refresh, officially the 5th Gen Intel Xeon Scalable Processors.

E-Cores vs. P-Cores

Unlike their 6900P series siblings announced for the third quarter, the Xeon 6700E have no AVX512 units, no AI-accelerating AMX units and can connect a maximum of DDR5-6400 with their eight memory channels. The Xeon 6900P can include up to three compute dies and then offer twelve DDR5 or faster MCRDIMM-8800 channels.

When it comes to media transcoding, the Xeon 6700E should have 30 percent more performance per watt than AMD's Epyc, according to Intel. Compared to a data center with five-year-old Xeon Scalable 82x0, they are said to achieve the same computing power with a third of the racks and save up to 84 GWh of electrical energy over a four-year interval.

Intel sees two 128-core P-core Xeons in the Bert Large AI model with DLBoost package and INT8 accuracy, allowing the AMX units to be used, 270 percent faster than a duo of AMD's Epyc-9654 CPUs with 96 cores each.

By manufacturing in Intel 4 technology (formerly known as 7 nm), Intel can squeeze up to 144 cores and four DDR5-6400 memory controllers onto one compute die in the Xeon 6766E and 6780E, which is flanked by two I/O dies. These include 88 PCIe 5.0 lanes, UPI links for connecting several processors and the four accelerators DSA, IAA, QAT and DLB familiar from the previous generations (see table). In systems with only one socket, the unused UPI links can be used to create a further 48 lanes for a total of 136 PCIe 5.0 lanes. The Xeon 6 processors can also connect devices via Compute Express Link 1 and 2.0. CXL can be used to connect cache-coherent computing accelerators as well as additional memory modules as CXL memory expanders and special SSDs.

Intel Xeon 6: 6700E mit E-Kernen für Zweisockel-Systeme
Modell	Kerne	Basistakt	Turbo*	L3-Cache	TDP	Speichergeschwindigkeit**	Beschleuniger (Anzahl)
6780E	144	2,2 GHz	3,0 GHz	108 MByte	330 Watt	DDR5-6400	DSA (2), IAA (2), QAT (2), DLB (2)
6766E	144	1,9 GHz	2,7 GHz	108 MByte	250 Watt	DDR5-6400	DSA (2), IAA (2), QAT (2), DLB (2)
6756E	128	1,8 GHz	2,6 GHz	96 MByte	225 Watt	DDR5-6400	DSA (2), IAA (2), QAT (2), DLB (2)
6746E	112	2,0 GHz	2,7 GHz	96 MByte	250 Watt	DDR5-5600	DSA (2), IAA (2), QAT (2), DLB (2)
6740E	96	2,4 GHz	3,2 GHz	96 MByte	250 Watt	DDR5-6400	DSA (2), IAA (2), QAT (4), DLB (4)
6731E***	96	2,2 GHz	3,1 GHz	96 MByte	250 Watt	DDR5-5600	DSA (2), IAA (2), QAT (2), DLB (2)
6710E	64	2,4 GHz	3,2 GHz	96 MByte	205 Watt	DDR5-5600	DSA (2), IAA (2), QAT (4), DLB (4)
* Allcore-Turbo ist gleich max. Turbo ** DDR5-5200 mit zwei DIMMs pro Kanal (2 DPC), *** nur für Systeme mit einer Fassung (1P) DSA: Data Streaming Accelerator, IAA: In-Memory Analytics Accelerator, QAT: QuickAssist Technology, DLB: Dynamic Load Balancer

A bewildering variety of models

Intel's Xeon 6 series server processors are more confusing than ever, despite the simplified naming scheme. Not only are they designed for two different versions, LGA4710 and LGA7529, they also have different core types - in addition to their number.

The first of these are the chiplets formerly known as Sierra Forest SP with many but slower E-cores, originally called efficiency cores. Seven models start as Xeon 67xxE with 64 to 144 cores. The finished package fits into the smaller of the two new LGA4710 sockets. CPUs for this socket can consume up to 350 watts, although this applies to the 86-core P versions that will be released later, as the Xeon 6700E can consume a maximum of 330 watts. The eight DDR5-6400 bars manage up to 410 GBytes per second, which is around 14 percent higher than the fifth-generation Xeon Scalable.

The Xeon 6900P will then follow in the third quarter. They will only fit into the larger of the two LGA7529 versions and will feature the faster P cores for the first time. Up to 128 cores per processor should be possible in three compute dies. The 6900 series can consume up to 500 watts. With a maximum of twelve memory channels (DDR5-6400) and optional support for MCR-8800 DIMMs, the maximum memory transfer rate is a whopping 845 GBytes per second per processor. In a 2P system, this adds up to over 1.6 TByte per second.

The other models will finally arrive in the first quarter of 2025, including the Xeon 6900E, which will have up to 288 cores with two Sierra Forest compute dies. This will be followed by the Xeon 6700P, Xeon 6500P and Xeon 6300P, each with P-cores for LGA4710 and a maximum of eight MCR-8000 DIMMs, as well as a SoC variant.

According to Intel's presentation, there will therefore be a number of different compute dies for E and P cores – the maximum number of active cores in products planned to date is shown in brackets: LCC (16), HCC (43), UCC/XCC (43) and ZCC (144). The only difference between UCC and XCC is that UCC is intended for LGA7529, XCC for LGA4720.

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