Intel's Lunar Lake mobile CPU: special lock with many new features

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Less than six months after the launch of Intel's mobile processor Meteor Lake aka Core Ultra 100, its successor Lunar Lake is already casting its shadow. Wait a minute: wasn't Meteor Lake supposed to be followed by Arrow Lake? Yes, that was once the plan. And Arrow Lake should still see the light of day before the end of the year so that, among other things, desktop PCs will finally get an Intel processor made up of chiplets. However, the competitive pressure has become too high: Microsoft has set the specifications of its premium label Copilot+ for AI-compatible notebooks so high that they were only met by Qualcomm's ARM processors from the Snapdragon X family at launch.

Of course, no brand new chip can be created in the few weeks since Copilot+ was unveiled. However, since Microsoft defined its specifications for Copilot+ not so long ago and communicated them to close partners such as the usual CPU manufacturers, Intel has massively prioritized development. This in turn was only possible because the chip was already well on its way and also outside the main development branch of core processors. The concept is roughly similar to that of Lakefield from a few years ago: Existing functional blocks are adapted and combined in a new manufacturing process to offer a special processor for particularly thin and energy-efficient mobile devices.

A typical chip development period of an estimated five years suggests that Intel started the Lunar Lake project when it was clear that Apple would switch from Intel's processors to its own ARM chips. Conceptually, Lunar Lake also fits perfectly into MacBook Air mobile devices, which are designed to work completely without fan noise and without a power supply unit for a long time. There are other reasons why at least one of these two desirable features will not be available for the time being - but more on that later.

Fewer chiplets

Like Meteor Lake, Lunar Lake uses a chiplet design, but with a completely different partitioning. Instead of a central SoC tile and three surrounding chiplets with I/O lines, the CPU and GPU cores, there are now only two, namely an I/O tile and a compute tile with all the function blocks of the CPU, GPU and NPU. In the past, this would have been called a separate processor and chipset and soldered onto a motherboard.

Intel's developers were allowed to leave the beaten track for Lunar Lake: Neither the compute tile nor the I/O tile are manufactured by Intel itself. Instead, they are produced in N3B (compute) and N6 (I/O) by the chip contract manufacturer TSMC - because Intel's in-house production division does not yet have an equivalent to the energy-efficient 3-nanometer process N3B in its portfolio. N3B is the same state-of-the-art process that Apple uses to manufacture its M4 chip family.

Only the underlying interposer, known as the base tile, which sits under the entire surface of the chiplets and couples them electrically, comes from Intel itself. As with Meteor Lake, an old 22-nanometer production line is sufficient for this. The packaging of Lunar Lake, i.e. the marriage between all chiplet components and the carrier, is carried out by Intel itself. Speaking of packaging: In one corner of the Lunar Lake interconnect, you can still find an almost square silicon filler tile. It is necessary in terms of signal quality and mechanical stability when installing a cooling system, but has no other functionality.

New cores everywhere

Intel uses brand-new units across the board for the blocks of the compute tile. While Meteor Lake still had eight E cores plus two additional LP-E cores in the SoC tile, Lunar Lake only has four in total. They have the new, much broader Skymont core architecture. Intel refers to the four-core cluster sometimes as E and sometimes as LP-E cores, which is confusing: the three-stage combination of LP-E, E and P cores first introduced with Meteor Lake has already become obsolete with Lunar Lake; as before, there are only the two stages E and P.

The four more powerful P cores are the debut of the new Lion Cove architecture. In Lunar Lake, Intel has dispensed with simultaneous multithreading, aka hyper-threading, which enables a 10 percent smaller footprint per core. According to Intel, this is a specific decision for Lunar Lake; in principle, Lion Cove would also allow hyper-threading. Compared to the Arrow Lake processors mentioned at the beginning, the size of the L2 cache has also been reduced from 3 to 2.5 MByte, and the Lunar Lake implementation also lacks extensions such as AVX512, which play a role more in the server world.

Instead of the familiar 100 MHz steps, which are packed on top of the base clock using Turbo, Lunar Lake provides a finer granular gradation in steps of 16.67 MHz. If the power budget is just not enough for 3.1 GHz, for example, a core previously had to be clocked down to 3.0 GHz - in future it can be around 3.067 GHz.

The integrated graphics unit is the first to get Xe2 cores, although desktop graphics cards of the second Arc generation Battlemage equipped with them are likely to arrive before the end of the year. The fine-tuning of the graphics cores should not only benefit games, but also AI applications. The new media engine can decode videos in the brand new H.266 format, also known as VVC, without CPU load.

Finally, the Neural Processing Unit (NPU) is also new - of course, otherwise Microsoft's Copilot+ specification of at least 40 TOPS in INT8 data format would remain unfulfilled. Intel specifies up to 48 TOPS for the Lunar Lake NPU (Meteor Lake: 11.5 TOPS). Intel achieves the increase in performance by tripling the number of AI computing units (so-called multiply-acculumate units or MACs for matrix calculation), and each one is also powered with four times the vector throughput.

Another prerequisite for Copilot+ is the presence of the Pluton security controller developed by Microsoft. Intel had previously refused to use this, but with Lunar Lake and Copilot+ there is no way around it - even if Intel does not refer to its implementation as Pluton, but as Partner Security Engine (PSE). However, Intel has not sidelined its own Silicon Security Engine (SSE), but has instead housed it in parallel. Among other things, it continues to take care of securing the boot process.

I/O integration

The I/O tile not only provides eight PCIe lines (four each in versions 4.0 and 5.0), but also three Thunderbolt 4 controllers and classic USB. As usual, a WLAN controller is integrated, which here masters state-of-the-art Wi-Fi 7 for the first time. Instead of the fully-fledged BE200 WLAN module, notebook manufacturers can use the simplified CNVi version BE201. Thanks to CNVi 3, data flows between BE201 and Lunar Lake at a higher speed to cope with the higher bandwidth of Wi-Fi 7.

The integrated Bluetooth adapter is no longer connected via USB, as has been the case since Centrino times, but via PCIe for the first time. However, this is not due to higher bandwidth requirements: Lunar Lake systems can instead transmit faster via Bluetooth when booting or waking up because they no longer have to wait for the USB controller. Either way, the PCIe host is at the top of the initialization sequence, for example because of SSDs or WLAN.

Less interesting for notebooks than for stationary mini PCs is the fact that Lunar Lake also includes a Gigabit Ethernet controller for cable connections.