Nvidia's memory future: 20 stacked DRAM chips on one GPU
High-Bandwidth Memory 5 is intended to further increase the number of memory layers. This requires modern stacking technology.
Blackwell GPU from Nvidia, still with eight HBM3e stacks next to the two computing chips.
(Image: c't / csp)
The memory manufacturers Samsung, SK Hynix and Micron want to stack even more DRAM chips on top of each other. With the fifth generation of the stacked DRAM High-Bandwidth Memory (HBM5), a version with at least 20 memory layers is to be released. This is reported by Trendforce, a market observer specializing in memory.
Current HBM3e devices use eight 24-gigabit dies – giving them a total capacity of 24 gigabytes. 12-fold stacked HBM3e modules, called 12-Hi, with 36 gigabytes have been announced. A 20-Hi variant with the same capacity per die would have a capacity of 60 gigabytes – However, the latter is likely to increase in parallel for even higher storage volumes.
(Image:Â Trendforce)
However, it will be several years before the product is ready for the market. Trendforce estimates that Nvidia wants to use HBM5 in the next generation. It will then no longer be located next to the GPU and connected via a silicon interposer, but will be mounted directly on the GPU.
Blackwell (B100 and B200) still use HBM3e. Nvidia has announced Rubin with eight HBM4 stacks for 2026; the improved version Rubin Ultra with 12 stacks will arrive in 2027. The Rubin successor with HBM4e would be due in 2028 and the successor with HBM5 in 2029 at the earliest.
(Image:Â Nvidia)
Hybrid bonding instead of solder balls
Until then, manufacturers will have to tackle production problems. Until now, they have been using solder balls, so-called micro-bumps, between the DRAM layers. Samsung and Micron rely on Thermal Compression Non-Conductive Film (TC-NCF) for stabilization: they apply a film to the individual chips, which melts under heat and pressure and thus bonds the layers together.
SK Hynix relies on so-called Mass Reflow-Molded Underfill (MR-MUF) to improve heat dissipation. The manufacturer describes it as follows: "Mass reflow is a technique in which the chips are bonded together by melting the bumps between the stacked chips. Molded Underfill fills the gaps between the stacked chips with a protective material to increase durability and heat dissipation. Using a combination of reflow and molding processes, MR-MUF attaches semiconductor chips to circuits and fills the space between the chips and the bump gaps with liquid epoxy molding compound (EMC)."
With even higher capacities and clock frequencies, however, the heat generated by the components increases. In addition, manufacturers have to save space to press the 20 memory layers into one component.
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The solution is said to be hybrid bonding, which AMD has previously used in its Ryzen X3D processors with stacked cache. All DRAM layers are then ground flat so that they adhere to each other without solder joints (bumps). To achieve this, manufacturers have to convert their packaging systems. Samsung presumably also wants to use this technology for NAND flash memory for SSDs.
16-fold stacked HBM4 and HBM4e stacks (16-Hi) could also appear with hybrid bonding if the manufacturers intend to gain experience with the technology in advance. However, it would obviously not yet be technically necessary.
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