Intel confirms 3D cache for new Xeons, not gaming CPUs
Xeons from the "Clearwater Forest" series with stacked cache are set to appear on the market in 2025. Nothing comparable is planned for desktop CPUs.
Intel's current Arrow Lake does not have a stack cache, nor was hyperthreading intended for it.
(Image: Intel)
In an interview, Intel's German press spokesman Florian Maislinger confirmed that his company is working on new processors with cache chips stacked on the CPU tiles. Similar to AMD's "3D V-Cache", this is intended to increase performance in certain applications. However, Intel is not targeting the comparatively small market of PC gamers, according to Maislinger, but rather professional applications in servers.
In the video interview with the YouTube channels "der8auer" and "Ben's Hardware", Maislinger said of the stacking technology: "Technologically, we still have it". And further, referring to the multi-die designs called "tile" at Intel instead of "chiplet" as at AMD: "Next year there will be a CPU for the first time that has a cache tile on it, but not in the desktop, or generally not in the client." The statements can be found from 1:19:00 in the video.
Instead, Maislinger continues, Intel's version of a stack cache will first appear in the Xeons codenamed "Clearwater Forest". As with AMD's current Ryzen 9800X3D, the cache die will be placed under the chip with the cores. To stick with Intel jargon, these two tiles are connected via Foveros Direct. Intel announced this stacking technology back in 2018 and it is now used in many of the manufacturer's designs, including the current Core Ultra 9 285K.
Between the lines, Maislinger made it obvious that the decision not to bring the 3D cache to desktop CPUs first is primarily an economic one: "This is not the huge mass market for us. You still have to realize that we sell many CPUs that are not necessarily used for gaming."
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Hyperthreading was not planned for Arrow Lake
Florian Maislinger also explained another much-discussed design decision for the current Arrow Lake generation, such as the 285K, in detail: the omission of hyperthreading (SMT) for the P cores. This requires chip area and energy and has fallen victim to the efficiency concept of Arrow Lake. Maislinger also contradicted the fact that hyperthreading was built into these CPUs, but was deactivated again after problems with it: "In fact, it is simply not there". However, this is not a fundamental decision, the Intel spokesperson continued. Future architectures could appear with hyperthreading again if it is worthwhile in the overall concept.
(nie)
