PCI Express 7.0 also chases 256 GByte/s via cable

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The industry body PCI SIG has finalized PCI Express 7.0: Members can download the specification in version 1.0. Various development teams have long since started work. However, series products are unlikely before 2028, just as there are still none with PCIe 6.0 from 2022.

The generation change to PCIe 7.0 will again double the data transfer rates. A single lane achieves 16 GByte/s per direction. With PCIe 7.0 x16, 256 GByte/s per direction are possible, i.e. up to 512 GByte/s in total. With PCIe 6.0 it is 128 or 256 GByte/s.

PCIe 6.0 introduces a signaling method with four-stage pulse amplitude modulation (PAM4), which PCIe 7.0 retains. Each transfer transmits two bits with four voltage levels, which requires more complex controllers. However, PCIe 6.0 and 7.0 remain downwards compatible.

PCIe is also the basis for Compute Express Link (CXL). This allows additional memory modules to be connected, for example.

PCIe cables internal & external

About a year ago, the PCI SIG announced the new CopprLink standard for electrical cable connections with PCIe 5.0 and 6.0. CopprLink is available in internal and external versions, the latter spanning a maximum of two meters and intended for coupling devices within a rack.

At this year's Computex IT trade fair, Molex also presented CopprLink with PCIe 7.0 – this specification is likely to follow.

PCI-Express-Kabelstandards, Stand Juni 2025
Name	PCIe-Generation	max. Länge	Steckverbinder
CopprLink extern	PCIe 5.0 & 6.0	2 m	SFF-TA-1032
CopprLink intern	PCIe 5.0 & 6.0	im System	SFF-TA-1016
PCIe External Cabling	PCIe 5.0	32 GT/s: 2 m, 8 GT/s: 3 m	SFF-8614
OCuLink	PCIe 3.0	8 GT/s: 2 m	diverse

CopprLink internal is used, for example, to connect backplanes in servers or for so-called flyover connections, which bridge longer distances on a circuit board. They are often cheaper than routing on the PCB, which requires more expensive PCB material with many layers due to the very high signal frequencies. Some current server boards have 20 copper layers and therefore cost more than 1000 euros.

Longer connections are possible via fiber optic cables (optical). There have been proprietary solutions for this for years. The PCI SIG wants to specify a standardized interface for PCIe 6.0 and 7.0. However, this does not yet refer to specific connectors, wavelengths and cable types.

The PCIe External Cabling specification is primarily intended for connecting SSDs (storage) and uses the SFF-8614 (MiniSAS-HD) connector. The older OCuLink was only specified up to PCIe 3.0 with 8 gigatransfers per second (GT/s).

First PCIe 6.0 chips

At Computex, Phison presented the first PCIe 6.0 controller for SSDs, the PT1601. The company Astera Labs already has PCIe 6.0 switches on offer. Micron presented an unnamed PCIe 6.0 SSD at the FMS storage trade fair in late summer 2024, without revealing a date for series production.

It is currently unclear which servers will be the first to launch with PCIe 6.0. AMD is unlikely to change its Epyc platforms until the end of 2026 at the earliest, with the switch to Zen 6 and TSMC's N2 manufacturing process. At Intel, the Xeon 7 aka Diamond Rapids for the huge LGA9324 version could also bring PCIe 6.0.

Ideas for PCIe 8.0

The PCI SIG has signaled that it will continue the roadmap: Initial trials (pathfinding) for PCIe 8.0 are already underway. The aim is to double the data signal rate compared to PCIe 7.0 to 256 gigatransfers per second.

Data transfer rates of PCIe and RAM (maximum transfer rate per direction)
Interface	Transfer rate
PCIe 7.0 x16	256 GByte/s
4 Kanäle DDR5-4800	154 GByte/s
PCIe 6.0 x16	128 GByte/s
2 channel DDR5-4800	77 GByte/s
PCIe 6.0 x8	64 GByte/s
PCIe 5.0 x16	64 GByte/s
1 channel DDR5-4800	38 GByte/s
PCIe 6.0 x4	32 GByte/s
PCIe 5.0 x8	32 GByte/s
PCIe 4.0 x16	32 GByte/s
1 channel DDR4-3200	26 GByte/s
PCIe 7.0 x1	16 GByte/s
PCIe 3.0 x16	16 GByte/s
PCIe 6.0 x1	8 GByte/s
PCIe 4.0 x4	8 GByte/s

(ciw)