Server CPU: Clearwater Forest comes as Xeon 6+ with up to 288 cores
Clearwater Forest doubles the number of computing cores for Intel servers of the Xeon 6 generation and fully utilises the I/O possibilities of the socket.
(Image: Intel)
The Xeon 6 server platform currently consists of two series. Xeon 6000P alias Granite Rapids has up to 128 P cores (performance), which are designed for high single-threaded performance. Its sister Xeon 6000E, codenamed Sierra Forest, offers normal server customers up to 144 E cores (efficiency). There is less computing power per core, but more cores per server socket. The problem for Intel is that the difference between 128 and 144 cores is not that great, and AMD's counterpart Epyc 9005, also known as Turin, has long since combined 192 Zen 5c cores in one processor. The Sierra Forest variant with 288 cores was only reserved for selected cloud hyperscalers.
Clearwater Forest, which Intel officially presented as the Xeon 6+ during its Tech Tour trade event, is now addressing this sore point. It offers up to 288 E-cores for a larger customer base and is therefore much more clearly differentiated from Granite Rapids. The E-cores use the new Darkmont architecture, which is also found in the Panther Lake notebook processor and for which Intel promises up to 17 percent higher computing performance (instructions per cycle, IPC) compared to its predecessor Crestmont from Sierra Forest. Independent benchmarks are not yet available. As with Panther Lake, the CPU chips in Clearwater Forest are also produced in Intel's own brand-new 18A process.
(Image:Â Intel)
Complex chiplet structure
However, the structure is much more complex, with a total of 29 chiplets: twelve CPU chiplets (Intel 18A), each with six clusters of four E-cores, are distributed across three base tiles (Intel 3). The latter are not passive but contain transistors, namely 192 MByte of last-level cache each and four DDR5 memory controllers, totaling 576 MByte cache and twelve memory controllers, as offered by Granite Rapids. The cache in the base tile corresponds to what AMD calls 3D V-Cache (also known as X3D).
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The base tiles are flanked by two identical I/O chiplets (Intel 7) for PCIe 5.0, CXL 2.0 and UPI 2.0, which Intel has adopted 1:1 from Granite Rapids. Here, the manufacturer plays the trump card of being able to use a chiplet not only several times, but also in different processors. A total of twelve small bridge chiplets (EMIB), which are embedded in the package substrate, connect the three base and two I/O tiles with each other. The entire package can consume between 300 and 500 watts.
Note: Intel invited the author to the Tech Tour to Arizona and covered the travel expenses.
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