Chip Research: Europe's Imec Gets High-NA EUV System

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The Belgian Interuniversity Microelectronics Centre (Imec) is significantly upgrading its semiconductor manufacturing together with European partners. An expansion of its cleanroom by 2000 square meters creates space for the latest generation of lithography systems: one that uses extreme ultraviolet light with high numerical aperture (High-NA EUV). The research center already operates previous Low-NA EUV systems; Imec previously only had access to a High-NA EUV system at ASML in Eindhoven.

Imec calls the expansion the NanoIC pilot line. In addition to Belgium, Fraunhofer from Germany, CEA-Leti from France, VTT from Finland, CSSNT from Romania, and the Tyndall National Institute from Ireland are involved. The money for the purchase and operation of the research semiconductor plant comes from these states and from the two EU funding pots Digital Europe and Horizon Europe. A High-NA EUV system from ASML is scheduled to arrive on March 18, 2026.

Research at the Forefront

While Europe's chip manufacturers have long since given up the race for the most advanced manufacturing processes, research continues to be pursued. Imec works with contract chip manufacturers like TSMC and Intel to develop new process generations. On the other hand, European chip designers gain access to process design kits (PDKs). Imec also works on specifications with suppliers.

Most recently, Imec introduced a PDK for the next generation A14 (formerly “1.4 nm”), enabling the first virtual chip designs. Another PDK is dedicated to embedded Dynamic Random Access Memory (DRAM) directly in processors or other chips. eDRAM is intended to bridge the gap between normal DRAM in memory modules and Static Random Access Memory (SRAM). While SRAM is particularly fast, it has a low capacity compared to DRAM.

The combination of DRAM and logic is complicated, as the manufacturing technology for DRAM has so far differed significantly from that for logic chips like processors. The designs developed with Imec can ultimately be adapted for other manufacturing processes. The PDKs are compatible with the widespread Electronic Design Automation (EDA) tools from Cadence and Synopsys.

High-NA EUV Further Refines Resolution

Lithography systems with High-NA EUV will become indispensable for the most advanced manufacturing processes by 2030. Intel plans to use High-NA EUV starting in 2027 with the 14A process, followed later by world market leader TSMC. Both companies are already operating such systems for testing purposes.

ASML from the Netherlands is the only company that can manufacture these systems, with German help among others: Zeiss supplies the necessary mirrors and lenses, Trumpf the lasers. A High-NA EUV system costs around 350 million euros, about twice as much as previous Low-NA EUV systems.

The numerical aperture refers to the amount of light captured. It is one of two factors with which chip manufacturers can increase exposure resolution. The other is the wavelength of the light. ASML relies on EUV light with a wavelength of 13.5 nanometers and already invests enormous effort in this.

A high-performance laser strikes 50,000 tin droplets two to three times per second, first to deform them and then to generate plasma that emits the necessary light. At 13.5 nanometers, ASML is already at the limit of X-ray light.

The industry is therefore focusing on the numerical aperture, which increases from 0.33 (Low-NA) to 0.55. This change brings its problems, which are, however, controllable. Externally, the dimensions are most striking: A High-NA EUV system like the Twinscan EXE:5200B is significantly taller than a Low-NA variant like the Twinscan NXE:3400C. This typically requires new, taller semiconductor plants.

Internally, even more complex optical systems are used. High-NA EUV requires larger mirrors. Only thanks to an anamorphic lens can the chip masks with the transistor blueprints reflect the light further.

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Vergleich Lithografie-Systeme High-NA vs. Low-NA (2 Bilder)

ASML Twinscan EXE:5200B (High-NA)

Real Benefit of High-NA EUV

ASML refers to the smallest possible structures as “critical dimensions.” Previous Low-NA EUV systems achieve 13 nm at best, while 8 nm is possible with High-NA EUV. According to ASML, transistors can be exposed approximately 1.7 times smaller, which almost triples the possible transistor density in one exposure process (1.7² ≈ 2.9).

The nanometer figures are not to be confused with the process names of contract chip manufacturers like TSMC, Samsung, and Intel. The current 2 nm generation, for example, contains no actual 2 nm structures; rather, the names have only been marketing for years. They are based on the so-called Dennard scaling, according to which each process generation should scale the transistor density by a factor of 0.7. Chip manufacturers simply continue to count the names; what results in, for example, 3 nm × 0.7 = 2 nm.

The actual structure size can be measured by various metrics. The center-to-center distance between the gates that control the current flow between source and drain is approximately 45 nm, including contacts, for TSMC's N2 process. This metric is also called Contacted Gate Poly Pitch (CPP). The gate itself can be 10 nm wide, depending on the transistor design. The center-to-center distance between adjacent metal lines, however, is said to be 20 nm. However, this Metal Pitch refers to the metal layers above the silicon that connect the transistors, not to the silicon itself.

Several trade-offs influence structures, including electrical properties and susceptibility to errors during exposure. Furthermore, the boundaries between different exposure techniques merge through multiple exposures (multi-patterning). TSMC, for example, deliberately continues to use multi-patterning because it is currently cheaper than using High-NA EUV systems.

(mma)