Japan invests another 4 billion US dollars in chip startup Rapidus

The Japanese company Rapidus Corporation is receiving further state funding from Japan. After initial subsidies, the state now intends to invest a total of the equivalent of 16 billion US dollars in the startup, which is already producing prototypes of 2-nanometer class wafers. Mass production is scheduled to begin in 2027.

As Bloomberg reports, Japanese Economy Minister Ryosei Akazawa pledged the increased subsidy last Saturday at a Rapidus event. This was held, among other things, to celebrate the opening of its new test center and the “Rapidus Chiplet Solutions” (RCS) division. Both are located next to Rapidus's first chip factory “IIM-1” (Innovative Integration for Manufacturing) in the city of Chitose on the island of Hokkaido.

Wafer, Testing and Packaging from a Single Source

Not far from there is also Rapidus's packaging factory, which the company has built on the Seiko Epson campus, according to its own announcement. Packaging involves mounting semiconductors onto substrates to create the finished components that can then be installed in devices. This means Rapidus will have all the essential steps of modern semiconductors in one place: wafer manufacturing, testing and dicing into individual chips, as well as packaging. Taiwan's market leader in high-end components, TSMC, operates similarly.

According to another recent announcement from Rapidus, there is already a “pilot line”, i.e., a production line for early prototypes of wafers and packages. For this, there is also a preliminary version of the “process design kit” (PDK), which allows chip designers who do not have their own manufacturing facilities to adapt their circuits to the manufacturing process. Rapidus also plans to release the general PDK soon, but has not yet provided a timeframe.

Goal: Mass production of the 2-nanometer class as early as 2027

In its new publications, the company has once again emphasized that mass production of complete 2-nanometer class components is scheduled to begin in 2027. As already reported in detail, all modern techniques such as Gate-All-Around transistors (GAAFET) and backside power delivery (backside power delivery) will be used. Such circuits are state-of-the-art today for high-performance processors needed for artificial intelligence or autonomous driving, for example. The 2-nanometer process is being developed together with numerous Japanese companies and research institutions. International partners such as IBM and the Fraunhofer Institutes are also involved.

(nie)