Chip lithography: Huawei aims to replace Moore's Law
Due to sanctions, Huawei is having difficulty further shrinking transistors. Short signal paths with stacked chips are intended to mask the problems.
(Image: Andreas Wodrich / heise medien)
Huawei is introducing an alternative evaluation method for scaling silicon chips: Instead of the constantly finer manufacturing density used until now, the signal transit times within the chips can be used as a benchmark, proposed He Tingbo, head of Huawei's semiconductor division HiSilicon, at the International Symposium on Circuits and Systems (ISCAS) in Shanghai over the weekend.
The ‘Tau Scaling Law’ proposed by Huawei could replace the decades-old ‘Moore’s Law’. The latter states that chip complexity doubles approximately every two years, primarily through ever finer manufacturing processes with more transistors per square millimeter of chip area. With the Tau Scaling Law, shortened signal transit times are to be the primary characteristic by which the performance of processors, AI accelerators, and other chips is measured.
Building on this, He announced the manufacturing principle „LogicFolding“: stacked logic chips. When stacked, signals can flow horizontally and vertically, which shortens the paths. Reduced resistances in the individual layers are intended to help further. Data movements consume a lot of energy; this approach therefore reduces electrical power consumption. It also favors clock frequencies.
The promises are big: By 2031, Huawei wants to catch up with its partners to the world's most advanced chip contract manufacturers. Specifically, Tingbo mentions a transistor density equivalent to 1.4-nanometer processes like Intel's 14A and TSMC's A14, which are expected to be ready for series production from 2028.
Empfohlener redaktioneller Inhalt
Mit Ihrer Zustimmung wird hier ein externes YouTube-Video (Google Ireland Limited) geladen.
Ich bin damit einverstanden, dass mir externe Inhalte angezeigt werden. Damit können personenbezogene Daten an Drittplattformen (Google Ireland Limited) übermittelt werden. Mehr dazu in unserer Datenschutzerklärung.
China's manufacturing technology is lagging behind
With this focus, however, Huawei also admits that it will not be able to catch up with the competition in classical chip lithography in the foreseeable future. This is not surprising, as the Dutch world market leader for chip exposure systems, ASML, is not allowed to sell its most modern equipment to China.
With older systems, Huawei and partners like the Chinese chip contract manufacturer SMIC are currently stuck in the 7-nanometer generation. Further improvements are possible, but reduce economic viability. The companies rely heavily on multiple exposures to achieve the necessary structures. However, each additional exposure increases the risk of defects. Chip production is already only profitable for SMIC & Co. through subsidies.
Videos by heise
TSMC & Co. are also stacking
Even with stacked chips, Huawei is unlikely to catch up with the competition. Because: TSMC, Intel, and Samsung also plan to stack logic chips in the foreseeable future. This has long been done with memory, for example in AMD's X3D processors with extra cache. From 2028, Nvidia plans to stack GPUs with TSMC.
Even today's design with multiple chiplets next to each other on a common substrate is a consequence of the slowing progress in chip manufacturing. This allows manufacturers to build larger chip constructs and optimize individual parts better. This approach has also been common in client processors for years. Intel's Core Ultra 300 (Panther Lake), for example, consists of three logic chiplets.
(Image: Christian Hirsch / heise medien)
One difference lies in the application field: Huawei aims to stack processors in smartphones in the near future. Such a Kirin processor for mobile devices is expected to be released as early as this autumn. Competitors outside of China currently only envision such an approach for server hardware, as stacking technology is expensive and complex. Cooling, for example, presents an obstacle that is particularly difficult to solve in compact devices like smartphones.
Meanwhile, Huawei also has to overcome disadvantages in stacking: ASML systems can align the silicon wafers on which the chips are exposed to within less than a nanometer. Unlike the fictional process names, this corresponds to a real value. The systems thus have an alignment accuracy of a few atoms. Chinese providers are lagging behind here.
(mma)
