AMD shows first wafer with 2-nanometer chips from TSMC
The next generation of Epyc processors is the first HPC product to use TSMC's N2 manufacturing technology. Pre-series wafers have already been completed.
AMD CEO Lisa Su and TSMC CEO C. C. Wei hold up a 2 nm wafer together. Unfortunately, the chip structures have been made unrecognizable.
(Image: AMD)
AMD is giving an unusually early preview of its next generation of processors for servers (codenamed Venice aka Epyc 9006). At least some offshoots are being created using production technology from TSMC's 2-nanometer generation N2. The basic design is already complete and TSMC has already exposed the first test wafers with the compute chiplets.
According to AMD, Venice is TSMC's first 2nm product for high-performance computing (HPC). TSMC defines HPC as anything that goes beyond a smartphone processor. However, it will still be a while before the market launch: there is talk of a presentation in 2026, probably closer to the second half of the year.
With N2, TSMC is switching from the long-established fin-shaped field-effect transistors (FinFETs) to gate-all-around transistors (GAAFETs). The chip contract manufacturer calls the latter nanosheets.
Epyc 9006 allegedly with up to 256 Zen 6 cores
AMD has not yet provided any further details. According to rumors, the Venice top model will be released with 256 Zen 6 cores, divided into eight compute chiplets with 32 cores each. The 32-core chiplet is to be produced using 2 nm technology. The rumors come from the YouTube channel “Moore's Law is Dead”, although its accuracy rate is mixed. The I/O die, including the memory controllers and PCI Express interfaces, will be produced separately, probably using older production technology.
AMD is reportedly launching a separate compute chiplet for desktop PCs for the first time since the introduction of the Zen architecture. It is said to contain 12 Zen 6 cores and will also roll off the production line at TSMC using 2 nm technology. New Ryzen top models would have 24 cores, plus possibly additional efficiency cores in the I/O die.
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AMD also has production in Arizona
In the same announcement on the TSMC cooperation, AMD also mentions production in the USA. Accordingly, AMD and TSMC have validated the first Epyc 9005 chiplets with 4 nm technology from the new semiconductor plant in Arizona. Primarily US customers should therefore receive Epyc 9005 processors that are at least partially “Made in US” in the future. This concerns the compute chiplets for the CPUs codenamed Turin, led by the 128-core Epyc 9755.
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