TSMC: This is what a high-end accelerator of the future looks like
Computing accelerators grow more complex with multi-chip designs. TSMC plans to stack logic chips while integrating power supply components into the package.
Nvidia already uses TSMC's Optical Engine for its current network chips. In the future, they will land on fast computing accelerators.
(Image: Nvidia)
The chip contract manufacturer TSMC wants to make progress in the production of fast computing accelerators for AI algorithms and high-performance computing (HPC). Complexity is set to increase significantly over the next few years. This includes stacked logic chips, optical transceivers and power supply technology integrated into the interposer.
Until now, GPUs such as those from AMD and Nvidia have consisted of several chiplets located next to each other on a silicon interposer. Fast memory modules of the high-bandwidth memory (HBM) type flank the logic dies on the same interposer. Manufacturers call this 2.5D stacking.
Up to now, an interposer has often been necessary to execute the many thousands of data paths between the logic chips and the HBM. An alternative way of connecting two chiplets on a carrier is to use small silicon bridge dies embedded in the carrier underneath the chiplets. This is called Intel Embedded Multi-Die Interconnect Bridge (EMIB).
New chip technology in the interposer
The interposer in particular is set to become more complex in future. A so-called redistribution layer (RDL) will take the place of a pure silicon variant. This contains isolated silicon areas that provide numerous data paths locally between two chiplets, similar to Intel's EMIB. TSMC calls this Local Silicon Interconnect (LSI).
In the future, TSMC will also integrate power management circuits (PMICs), coils and capacitors (embedded deep trench capacitor, eDTC) directly into the interposer. Other capacitors will move to the RDL. Even today, the fastest AI accelerators consume more than one kilowatt, Nvidia's B200 around 1200 watts. By 2030, electrical power consumption is expected to increase many times over. According to TSMC, this will require parts of the power supply to be built directly into the chip designs (Integrated Voltage Regulation, IVR). The idea is not fundamentally new; Intel already used FIVR 11 years ago.
(Image:Â Taiwan Semiconductor Manufacturing Co., Ltd.)
More stacks
In future, the manufacturer wants to stack logic chips on top of each other. This could be compute chiplets with arithmetic units and I/O dies with memory and PCIe controllers or several compute chiplets. TSMC cites combinations of the A14 and N2 production processes as examples, but in general all possible process variants are conceivable.
TSMC continues to favor fast memory chips alongside logic chips, but in principle they could also be stacked. So far, AMD has done this with its CPUs with cache dies.
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Taiwan Semiconductor Manufacturing Co., Ltd.
)Optical interconnects directly on the chip constructs are to become the standard for fast AI accelerators in the future in order to connect them together in a network via fiber optics. To this end, TSMC packs duos of optical transceivers and electrical circuits to translate the optical signals onto the carrier. The product is called TSMC Optical Engine. The logic chips continue to use electrons for data transmission. Nvidia is already working with TSMC on this technology.
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Wafer processors
If a manufacturer wants to go all out, there are also systems-on-wafer (SoW). The SoW-X expansion stage should be ready for series production in 2027: a wafer serves as a huge carrier for countless chips, including logic chips, I/O dies and memory modules. An example schematic shows 16 compute dies with 64 HBM components. The previous Wafer Scale Engine (WSE-3) from Cerebras with SoW technology does not use stacked chips. Instead, TSMC exposes all arithmetic units, SRAM and other components on a single wafer.
(Image:Â Taiwan Semiconductor Manufacturing Co., Ltd.)
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